121,936 research outputs found

    Two-Level Lattice Neural Network Architectures for Control of Nonlinear Systems

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    In this paper, we consider the problem of automatically designing a Rectified Linear Unit (ReLU) Neural Network (NN) architecture (number of layers and number of neurons per layer) with the guarantee that it is sufficiently parametrized to control a nonlinear system. Whereas current state-of-the-art techniques are based on hand-picked architectures or heuristic-based search to find such NN architectures, our approach exploits a given model of the system to design an architecture; as a result, we provide a guarantee that the resulting NN architecture is sufficient to implement a controller that satisfies an achievable specification. Our approach exploits two basic ideas. First, we assume that the system can be controlled by a Lipschitz-continuous state-feedback controller that is unknown but whose Lipschitz constant is upper-bounded by a known constant; then using this assumption, we bound the number of affine functions needed to construct a Continuous Piecewise Affine (CPWA) function that can approximate the unknown Lipschitz-continuous controller. Second, we utilize the authors' recent results on the Two-Level Lattice (TLL) NN architecture, a novel NN architecture that was shown to be parameterized directly by the number of affine functions that comprise the CPWA function it realizes. We also evaluate our method by designing a NN architecture to control an inverted pendulum

    A 0.18ÎŒm CMOS 300MHz Current-Mode LF Seventh-order Linear Phase Filter for Hard Disk Read Channels

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    “This material is presented to ensure timely dissemination of scholarly and technical work. Copyright and all rights therein are retained by authors or by other copyright holders. All persons copying this information are expected to adhere to the terms and constraints invoked by each author's copyright. In most cases, these works may not be reposted without the explicit permission of the copyright holder." “Copyright IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE.”A 300MHz CMOS seventh-order linear phase gm-C filter based on a current-mode multiple loop feedback (MLF) leap-frog (LF) structure is realized. The filter is implemented using a fully-differential linear operational transconductance amplifier (OTA) based on a source degeneration topology. PSpice simulations using a standard TSMC 0.18ÎŒm CMOS process with 2.5V power supply have shown that the cut-off frequency of the filter can be tuned from 260MHz to 320MHz and dynamic range is about 66dB. Group delay ripple is approximately 4.5% over the whole tuning range and maximum power consumption is 210mW

    A 0.18ÎŒm CMOS 9mW current-mode FLF linear phase filter with gain boost

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    “This material is presented to ensure timely dissemination of scholarly and technical work. Copyright and all rights therein are retained by authors or by other copyright holders. All persons copying this information are expected to adhere to the terms and constraints invoked by each author's copyright. In most cases, these works may not be reposted without the explicit permission of the copyright holder." “Copyright IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE.”The design and implementation of a CMOS continuous-time follow-the-leader-feedback (FLF) filter is described. The filter is implemented using a fully-differential linear, low voltage and low power consumption operational transconductance amplifier (OTA) based on a source degeneration topology. PSpice simulations using a standard TSMC 0.18 mum CMOS process with 2 V power supply have shown that the cut-off frequency of the filter ranges from 55 MHz to 160 MHz and dynamic range is about 45 dB. The group delay is less than 5% over the whole tuning range; the power consumption is only 9 mW

    Synchronization in an array of linearly stochastically coupled networks with time delays

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    This is the post print version of the article. The official published version can be obtained from the link - Copyright 2007 Elsevier LtdIn this paper, the complete synchronization problem is investigated in an array of linearly stochastically coupled identical networks with time delays. The stochastic coupling term, which can reflect a more realistic dynamical behavior of coupled systems in practice, is introduced to model a coupled system, and the influence from the stochastic noises on the array of coupled delayed neural networks is studied thoroughly. Based on a simple adaptive feedback control scheme and some stochastic analysis techniques, several sufficient conditions are developed to guarantee the synchronization in an array of linearly stochastically coupled neural networks with time delays. Finally, an illustrate example with numerical simulations is exploited to show the effectiveness of the theoretical results.This work was jointly supported by the National Natural Science Foundation of China under Grant 60574043, the Royal Society of the United Kingdom, the Natural Science Foundation of Jiangsu Province of China under Grant BK2006093, and International Joint Project funded by NSFC and the Royal Society of the United Kingdom
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